1. Field of the Invention
The present invention relates to I/O buffers for integrated circuits, and more particularly to a 5 volt tolerant I/O buffer, i.e., an I/O buffer to which 5 volts may be applied through a pad of the I/O buffer without adversely affecting circuit operation.
2. State of the Art
In integrated circuit technology, devices in different integrated circuit (IC) packages are interconnected to one another at I/O pads associated with each IC package. I/O pads are associated with electrical circuits which perform a desired function to interface with other IC packages or electrical devices. An I/O pad may be associated with electrical circuits which generate output signals and apply the signals to the I/O pad for external devices to sense and process accordingly. Alternatively, an I/O pad may be associated with electrical circuits which sense the logic state of signals applied to the I/O pad by external electrical circuits or IC packages. I/O pads are frequently "bidirectional" in the sense that they may be used at different times for the sensing of input signals to the IC package or for the application of output signals from the IC package. Electrical output signals are applied to an I/O pad via electrical circuits within the IC package associated with the I/O pad. Similarly, electrical input signals are received as input signals from an I/O pad by associated electrical circuits within the IC package which "sense" the signal level and operate accordingly.
It is common for such interconnected circuits to utilize standard voltage levels to represent logic states "0" and "1" (or "ON" and "OFF"). Common standard voltage levels in the past have been 0 volts (plus or minus a threshold value) to represent one logic state and 5 volts (plus or minus a threshold value) to represent the other logic state. As new IC manufacturing technologies evolve, the voltage levels used may change. For example, in the manufacture of many current IC devices using submicron semiconductor fabrication processes, the semiconductor industry has begun to standardize on 3 volt (more precisely, 3.3 volt, plus or minus a threshold value) in place of 5 volt signal levels to improve performance and reduce power dissipation. The lower voltage level permits reduced thickness in transistor gate oxide materials to thereby reduce switching time of transistor gates and improve performance of the switching circuitry.
Mixed mode operation occurs when circuits operating at 3 volts and 5 volts are coupled together. A simple example is described by coupling 3 and 5 volt digital logic circuits to a common bus. The logic circuits will typically have tristate buffers to avoid contention on the bus. Both 3 and 5 volt circuit types can read and write data to the bus but the magnitudes of the logic one levels of each will differ depending on the operating voltage. A problem with mixed mode operation is that a 3 volt tristate buffer may not be able to withstand a 5 volt signal without damaging itself or producing large leakage currents.
A standard tristate buffer design (for non-mixed mode operation) suffers from a high current drain problem at the drain of the P channel output device when the bus voltage exceeds its supply voltage. The bulk (N type region) of the P channel output device couples to the supply voltage of the tristate buffer (for example, 3 volts). The drain (P type) of the P channel output device couples to the bus. The PN diode formed by the bulk and drain becomes forward biased when the voltage on the bus reaches a diode drop above its supply voltage.
Referring to FIG. 1, consider an I/O buffer driven by a 3 volt power supply and connected to a bus which operates at 0 volts, 3 volts and 5 volts. when the I/O buffer is output disabled, the bond pad voltage can go up to 5 volts. In this condition, extra leakage current will flow from the bond pad to the 3 volt power supply. Two possible paths for this leakage current are shown in FIG. 1. To reduce the body effect of the transistor, the bulk voltage should be equal to the source voltage. Normally this is achieved by tying bulk to the source. In this case, current will leak into the source through the parasitic diode between the drain of the transistor P1 and bulk, whenever the voltage difference between the pad and VDD is more than a diode drop. The second current leak is through the transistor P1 itself. In the output disabled condition, the gate of P1 is at 3 volts. A 5 volt signal at the pad will turn the transistor P1 on, leaking current into VDD. In order to make the I/O buffer 5 volt tolerant, these two current paths should be blocked.
Various 5 volt tolerant I/O buffer circuits have been proposed. Examples of such circuits are described in U.S. Pat. No. 5,451,889 and U.S. Pat. No. 5,528,447, both of which are incorporated herein by reference. The proposed circuits are, in general, either unduly complicated or rely on logic that is pad driven during an output enabled state. In the latter instance, although steady state performance of the circuit may be acceptable, the circuit switches more slowly than is necessary.